Design Review for ASICs

(before CDR)

V0.1

Definition

The objectives of the Design Review for ASICs held before the project PDR are as follows:

Review and validate the detailed design of the ASICs from technical standpoint
Ensure that the detailed design of ASICs meets all project requirements (incl. Marketing, Manufacturing and Material)
Clearly identify the risks related to ASICs and possible contingencies
Review status of ASICs and S/W work to ensure good co-ordination with H/W
Perform last sanity check on refined plans (schedule and resources) for ASICs implementation work to be conducted during Implementation Stage

Questions

Technical assessment

Does the detailed design of ASICs meet the product specifications?
Have the key risks related to ASICs been correctly identified and evaluated?
What contingencies can we propose against those risks?
Are the ASIC verification plans appropriate given the ASICs detailed design?
Are the test programs for ASICs (Unit, Integration) appropriate?
What are the open issues which need to be addressed regarding ASICs?

Cross-functional check

Does the ASICs design support the Manufacturing requirements?
Does the ASICs design support the Manufacturing Test requirements?
Are there any issues related to the current BOM from the sourcing standpoint?

ASICS schedule and resources

Is the proposed schedule until ASICs RTM appropriate?
Are the corresponding resources appropriate (# of people, type of skills)?
Have we identified additional ASIC risks (technical, cost, schedule basis)?
From a ASICs standpoint, are we ready to proceed further (module coding, RTL, RTM)?

Input

Marketing

MRD (remains a living document after the Planning & Specification Stage Review but with limited changes expected)

Service

Serviceability objectives
Product Service Plan

R&D

System Architecture

Architecture reference model

ASIC Design

Model definition
Model diagram
Pinout
Programmer reference model
Block diagrams
Pseudo code
Simulation results

ASIC Verification

All 4 stages of verification ready
Results of before-tape-out unit and integration testing
List of bugs

H/W design

Interface between H/W - H/W, H/W - S/W, H/W - ASICs, H/W - system
95% Jedec files completed
Electrical schematics ready
Timing, thermal (70% of work only) and performance analysis
Mechanical drawings
Preliminary placement
BOM
Layout recommendations (size, # of layers, special line, list of critical signal files)
Utilities for testing
Board programmer reference model
Quality reliability and compliance
Design documentation (95%)

S/W design

SRS
S/W design document (for each block)
Management interfaces specifications (MIBs and relevant NMS application, LMA)
Detailed performance estimations
S/W integration and module test plan
Updated S/W development plan
S/W configuration management tool and usage methodology ready

Engineering Prototypes

Build plans for prototypes
Usage plans for prototypes (R&D, Manufacturing, Safety regulations)

R&D Test

Final Unit / Integration Test programs
Final Engineering Test programs
Engineering Test tools and equipment list
Initial System and Alpha Test procedures
Test environment set-up, external labs ordered

Manufacturing

Test Vehicle results and required action items
Progress report on DFX activities (completed and remaining)
Manufacturing costs, NREs and GM analysis
Material Flow
Updated Manufacturing Plan (Gantt chart)

Manufacturing Test

Final placement of test points
Updated Test equipment availability plan
Frame of S/W testing

Materials

List of qualified vendors

Finance

Estimates of product GM in production (on a per component basis)

Deliverables
ASICs design validated
List of open issues related to ASICs design
Updated ASICs schedule for RTL, RTM
Additional ASIC resources identified (if any needed)

Definition	The objectives of the Design Review for ASICs held before the project PDR are as follows: Review and validate the detailed design of the ASICs from technical standpoint Ensure that the detailed design of ASICs meets all project requirements (incl. Marketing, Manufacturing and Material) Clearly identify the risks related to ASICs and possible contingencies Review status of ASICs and S/W work to ensure good co-ordination with H/W Perform last sanity check on refined plans (schedule and resources) for ASICs implementation work to be conducted during Implementation Stage
Questions	Technical assessment Does the detailed design of ASICs meet the product specifications? Have the key risks related to ASICs been correctly identified and evaluated? What contingencies can we propose against those risks? Are the ASIC verification plans appropriate given the ASICs detailed design? Are the test programs for ASICs (Unit, Integration) appropriate? What are the open issues which need to be addressed regarding ASICs? Cross-functional check Does the ASICs design support the Manufacturing requirements? Does the ASICs design support the Manufacturing Test requirements? Are there any issues related to the current BOM from the sourcing standpoint? ASICS schedule and resources Is the proposed schedule until ASICs RTM appropriate? Are the corresponding resources appropriate (# of people, type of skills)? Have we identified additional ASIC risks (technical, cost, schedule basis)? From a ASICs standpoint, are we ready to proceed further (module coding, RTL, RTM)?
Input	Marketing MRD (remains a living document after the Planning & Specification Stage Review but with limited changes expected) Service Serviceability objectives Product Service Plan R&D System Architecture Architecture reference model ASIC Design Model definition Model diagram Pinout Programmer reference model Block diagrams Pseudo code Simulation results ASIC Verification All 4 stages of verification ready Results of before-tape-out unit and integration testing List of bugs H/W design Interface between H/W - H/W, H/W - S/W, H/W - ASICs, H/W - system 95% Jedec files completed Electrical schematics ready Timing, thermal (70% of work only) and performance analysis Mechanical drawings Preliminary placement BOM Layout recommendations (size, # of layers, special line, list of critical signal files) Utilities for testing Board programmer reference model Quality reliability and compliance Design documentation (95%) S/W design SRS S/W design document (for each block) Management interfaces specifications (MIBs and relevant NMS application, LMA) Detailed performance estimations S/W integration and module test plan Updated S/W development plan S/W configuration management tool and usage methodology ready Engineering Prototypes Build plans for prototypes Usage plans for prototypes (R&D, Manufacturing, Safety regulations) R&D Test Final Unit / Integration Test programs Final Engineering Test programs Engineering Test tools and equipment list Initial System and Alpha Test procedures Test environment set-up, external labs ordered Manufacturing Test Vehicle results and required action items Progress report on DFX activities (completed and remaining) Manufacturing costs, NREs and GM analysis Material Flow Updated Manufacturing Plan (Gantt chart) Manufacturing Test Final placement of test points Updated Test equipment availability plan Frame of S/W testing Materials List of qualified vendors Finance Estimates of product GM in production (on a per component basis)
Deliverables	ASICs design validated List of open issues related to ASICs design Updated ASICs schedule for RTL, RTM Additional ASIC resources identified (if any needed)